CPU Architectures
Deep dives into x86, ARM, and RISC-V architectures - registers, instruction sets, and design philosophy.
Recommended Prerequisites
These are recommendations - you can start this track at any time.
About this track
Deep dives into x86, ARM, and RISC-V architectures - registers, instruction sets, and design philosophy.
The CPU Architectures track collects 7 modules and 28 lessons into a single ordered path. Each module ends with a checkpoint quiz; passing the checkpoint unlocks the next module so you can track your progress without guessing whether the material has stuck.
You start with "x86 Architecture Deep Dive" and finish on "Multi-Core & Coherence". The whole track sits inside the Systems Deep Dives area of the curriculum, so the writing assumes the prerequisites listed above and skips ground that an earlier track has already covered.
What this track covers
- x86 Architecture Deep Dive — The architecture that powers most desktops and servers. Explore x86's CISC heritage, its register set, addressing modes, and the legacy design decisions that shaped modern computing.
- ARM Architecture Deep Dive — The architecture that powers nearly every smartphone and tablet on Earth. Explore ARM's RISC philosophy, its elegant instruction encoding, and why efficiency makes it king of mobile and embedded.
- RISC-V Architecture Deep Dive — The open-source ISA changing everything. Explore RISC-V's clean-sheet design, its modular extension system, and why being free and open matters for the future of computing.
- CPU Pipeline & Microarchitecture — Understand how modern CPUs actually execute instructions - pipelines, branch prediction, out-of-order execution, and superscalar design.
- SIMD & Vector Processing — Harness data parallelism with SIMD instructions, program with intrinsics, apply SIMD to real-world problems, and understand GPU computing fundamentals.
- Processor Security Features — Explore hardware security mechanisms: secure enclaves, pointer authentication, memory tagging, side-channel mitigations, and trusted platform modules.
- Multi-Core & Coherence — Understand multi-core architecture, cache coherence protocols, memory consistency models, and heterogeneous computing with specialised accelerators.
How the track works
Every lesson is a short page with diagrams, runnable examples, and the kind of edge-case footnotes you usually only find in textbooks. Where it makes sense, the lesson is paired with a CPU simulation or a coding challenge so you can poke at the idea instead of just reading about it.
The lessons themselves are free to read with a free account. The 7 checkpoint quizzes that gate the next module are also free, as are the lesson IDE and CPU simulations. Optional 777-tier tools — the step-through debugger, decompiler, ROP gadget builder, heap visualiser, and exploit labs — sit alongside the lessons but are not required to follow the track from start to finish.
You can jump in at any point. Be Bitwise is built around a free forever curriculum, with no time limits and no expiring access. Pick the next lesson when you have an hour; come back when you do not.